1. Field of the Invention
This invention relates generally to integrated circuit (IC) capacitors, and more particularly to a layered capacitor architecture and fabrication method.
2. Description of the Related Art
Integrated circuits frequently require the use of one or more capacitive devices, which serve numerous purposes in both analog and digital circuits. For example, a capacitor can provide an integration function, serve as part of a filter design, act as an energy or data storage device, or provide a bypass or decoupling capacitance on an IC.
However, a capacitor integrated on an IC die is necessarily small, and thus inherently limited with respect to the amount of capacitance it can provide. At the same time, modern electronic circuits require devices with ever greater capacitances. However, as integration density increases, chip space for large capacitors is less readily available. Numerous capacitor designs are known for providing increased capacitance by increasing the area of their conductive plates, and/or reducing the thickness of their dielectric layer. However, these devices remain limited in their ability to provide high capacitance values, due to the limited chip area typically allotted for capacitors.
Off-chip devices can provide large capacitances, but often cannot be used due to their size, as well as the length and number of connections required and the attendant signal propagation times, resistive voltage drops and connection inductances.